Digital circuits such as microprocessors, memory circuits, busses and other devices are frequently synchronous circuits in which operations may be synchronized by one or more clock signals. A clock signal is typically a periodic signal having a particular frequency. FIG. 1 shows an example of a known device 10 having logic circuitry 12 which is synchronized by a clock signal A. The device 10 may also have additional logic circuitry 14 which is synchronized by a clock signal B which may be at a different frequency than that of clock signal A. Thus, the logic circuitry 12, 14 can be said to operate in different clock domains, here, clock A domain and clock B domain, respectively.
A device such as device 10 may have separate clock domains for a variety reasons. For example, if the device 10 is part of a portable, battery operated device, the clock signal A may have a frequency substantially lower than that of clock signal B. Hence, logic circuitry 12 may, in some applications, be operated at a reduced power level as compared to logic circuitry 14, to extend effective battery time.
The circuitry of the various clock domains of a device often do not operate completely independently of the operations of the other clock domains. Thus, data may be transferred from one clock domain to another clock domain. The device 10 has a register 16 which may be loaded with data for transfer to the clock B domain. FIGS. 2a and 2b are timing diagrams illustrating a sequence of data words, Word0, Word1, . . . Wordn loaded into the register 16. In that the register 16 is in the clock A domain, the register 16 is clocked by the clock signal A. In this example, each data word is available for a full period of clock signal A as shown in FIGS. 2a, 2b. 
A data word provided by the register 16 of the clock A domain may be loaded by a register 18 of the clock B domain. In that the register 18 is in the clock B domain, the register 18 is clocked by the clock signal B. In the example of FIG. 2a, the clock signal B has exactly twice the frequency of clock signal A. Thus, the period of the clock signal A is an integral multiple of (here two times) the period of the clock signal B. Accordingly, if the register 18 is triggered to load data from the register 16 on the leading edge 20, for example, of the clock signal B, a data word may be loaded from the register 16 on the leading edge of each clock signal A, as indicated by dashed lines 22 in FIG. 2a. Alternatively, if the register 18 is triggered to load data from the register 16 on the leading edge 24, for example, of the clock signal B, a data word may be loaded from the register 16 on the trailing edge of each clock signal A as indicated by dashed lines 26 in FIG. 2a. 
FIG. 2b shows another example in which the period of the clock signal A is not an integral multiple of the period of the clock signal B. In this example, the period of the clock signal A is 5/3 that of the clock signal B. If the register 18 is triggered to load data from the register 16 on the leading edges 20, 24 for example, of the clock signal B, it is seen that the point within the clock signal A at which the data word is loaded into the register 18, shifts from pulse to pulse as indicated by the series of dashed lines 30a, 30b . . . 30n. Eventually, the cycle repeats such that at dashed line 30n, the point within the clock signal A at which the data word is loaded into the register 18 is the same as that of the dashed line 30a. In this example, the cycle is fifteen times the period of the clock B.